{
	"components": {
		"PC":         {"type": "PC", "x": 40, "y": 250, "in": "NewPC", "out": "PC", "write": "Write", "desc": {"default": "Contains the address of the instruction being executed.\nThe address is updated (with the value at the input) at the clock transition if Write is active.", "pt": "Contém o endereço da instrução a ser executada.\nO endereço é actualizado (com o valor da entrada) na transição do relógio se Write estiver activo."}},
		"ForkPC":     {"type": "Fork", "x": 80, "y": 265, "size": 32, "in": "In", "out": ["Out1", "Out2"]},
		"PCAdder":    {"type": "Add", "latency": 50, "x": 110, "y": 158, "in1": "In1", "in2": "In2", "out": "PC+4", "desc": {"default": "Calculates the address of the next sequential instruction.", "pt": "Calcula o endereço da instrução sequencial seguinte."}},
		"Const4":     {"type": "Constant", "x": 85, "y": 173, "out": "Out", "val": 4, "size": 32},
		"ForkPCAdder":{"type": "Fork", "x": 155, "y": 175, "size": 32, "in": "In", "out": ["Out1", "Out2"]},
		"MuxPC":      {"type": "Multiplexer", "latency": 15, "x": 15, "y": 248, "size": 32, "sel": "PCSrc", "in": ["0", "1"], "out": "Out", "desc": {"default": "Selects PC+4 or the branch address as the new PC.", "pt": "Selecciona o PC+4 ou o endereço de branch como novo PC."}},
		"InstMem":    {"type": "InstructionMemory", "latency": 300, "x": 90, "y": 215, "in": "Address", "out": "Instruction"},
		
		"IF/ID":      {"type": "PipelineRegister", "x": 180, "y": 110, "write": "Write", "flush": "Flush", "regs": {"NewPC": 32, "Instruction": 32}},
		
		"DistInst":   {"type": "Distributor", "x": 200, "y": 250, "in": {"id": "Instruction", "size": 32}, "out": [{"msb": 31, "lsb": 26}, {"msb": 25, "lsb": 21}, {"msb": 20, "lsb": 16},   {"msb": 15, "lsb": 11}, {"msb": 15, "lsb": 0}]},
		"ForkRt":     {"type": "Fork", "x": 220, "y": 265, "size": 5, "in": "In", "out": ["Out1", "Out2"]},
		"RegBank":    {"type": "RegBank", "latency": 100, "x": 260, "y": 215, "num_regs": 32, "read_reg1": "ReadReg1", "read_reg2": "ReadReg2", "read_data1": "ReadData1", "read_data2": "ReadData2", "write_reg": "WriteReg", "write_data": "WriteData", "reg_write": "RegWrite", "forwarding": true, "const_regs": [{"reg": 0, "val": 0}], "desc": {"default": "Holds all the MIPS registers and provides read/write to them.\nThe values of the ReadReg1 and ReadReg2 registers are read to the outputs.\nWriteData is written to the WriteReg register at the clock transition if RegWrite is enabled.\nWhen the same register is read from and written to in the same clock cycle, this register bank also forwards the written value to the output.", "pt": "Contém todos os registos do MIPS e fornece acesso de leitura/escrita aos mesmos.\nOs valores dos registos ReadReg1 e ReadReg2 são lidos para as saídas.\nWriteData é escrito para o registo WriteReg na transição do relógio se RegWrite estiver activo.\nQuando o mesmo registo é lido e escrito no mesmo ciclo de relógio, este banco de registos também encaminha o valor escrito para a saída."}},
		"Control":    {"type": "ControlUnit", "latency": 50, "x": 230, "y": 70, "in": "Opcode"},
		"ExtendImm":  {"type": "SignExtend", "x": 280, "y": 330, "in": {"id": "In", "size": 16}, "out": {"id": "Out", "size": 32}, "desc": {"default": "Extends the instruction's immediate value from 16 to 32 bits, in the case it is an I-type instruction.", "pt": "Estende o valor imediato da instrução de 16 para 32 bits, no caso de ser uma instrução do tipo I."}},
		"ForkRs":     {"type": "Fork", "x": 230, "y": 235, "size": 5, "in": "In", "out": ["Out1", "Out2"]},
		"HazardUnit": {"type": "HazardDetectionUnit", "latency": 50, "x": 230, "y": 10, "id_ex_mem_read": "ID/EX.MemRead", "id_ex_rt": "ID/EX.Rt", "if_id_rs": "IF/ID.Rs", "if_id_rt": "IF/ID.Rt", "stall": "Stall"},
		"ForkStall":  {"type": "Fork", "x": 265, "y": 5, "size": 1, "in": "In", "out": ["Out1", "Out2"]},
		"ForkRs2":    {"type": "Fork", "x": 215, "y": 235, "size": 5, "in": "In", "out": ["Out1", "Out2"]},
		"ForkRt3":    {"type": "Fork", "x": 220, "y": 255, "size": 5, "in": "In", "out": ["Out1", "Out2"]},
		"NotStall":   {"type": "Not", "x": 175, "y": 2, "in": "Stall", "out": "Write"},
		"ForkWrite":  {"type": "Fork", "x": 190, "y": 50, "size": 1, "in": "In", "out": ["Out1", "Out2"]},
		
		"ID/EX":      {"type": "PipelineRegister", "x": 390, "y": 110, "regs": {"ReadData1": 32, "ReadData2": 32, "NewPC": 32, "Imm": 32, "Rs": 5, "Rt": 5, "Rd": 5, "RegDst": 1, "ALUOp": 2, "ALUSrc": 1, "Branch": 1, "MemRead": 1, "MemWrite": 1, "MemToReg": 1, "RegWrite": 1}, "desc": {"default": "Register that separates two pipeline stages.\nThe values that transition to the next stage are stored here temporarily.\nIf Flush is active, all values are set to zero, inserting a NOP instruction.", "pt": "Registo que separa duas etapas do pipeline.\nOs valores que transitam para a próxima etapa são armazenados aqui temporariamente.\nSe Flush estiver activo, todos os valores são colocados a zero, inserindo uma instrução NOP."}},
		
		"ForkReg":    {"type": "Fork", "x": 445, "y": 281, "size": 32, "in": "In", "out": ["Out1", "Out2"]},
		"MuxFwdA":    {"type": "Multiplexer", "latency": 15, "x": 425, "y": 230, "size": 32, "sel": "ForwardA", "out": "Out", "in": ["0", "1", "2"], "desc": {"default": "Selects, in conjunction with the forwarding unit, if the value of the 1st register comes from the register bank or if it's forwarded from one of the next stages.", "pt": "Selecciona, em conjunto com a unidade de atalhos, se o valor do 1º registo vem do banco de registos ou se é encaminhado de uma das etapas seguintes."}},
		"MuxFwdB":    {"type": "Multiplexer", "latency": 15, "x": 425, "y": 275, "size": 32, "sel": "ForwardB", "out": "Out", "in": ["0", "1", "2"], "desc": {"default": "Selects, in conjunction with the forwarding unit, if the value of the 2nd register comes from the register bank or if it's forwarded from one of the next stages.", "pt": "Selecciona, em conjunto com a unidade de atalhos, se o valor do 2º registo vem do banco de registos ou se é encaminhado de uma das etapas seguintes."}},
		"ForkEXR2":   {"type": "Fork", "x": 421, "y": 299, "size": 32, "in": "In", "out": ["Out1", "Out2"]},
		"ForkMEMR2":  {"type": "Fork", "x": 416, "y": 291, "size": 32, "in": "In", "out": ["Out1", "Out2"]},
		"MuxReg":     {"type": "Multiplexer", "latency": 15, "x": 455, "y": 270, "size": 32, "sel": "ALUSrc", "out": "Out", "in": ["0", "1"], "desc": {"default": "Selects the value of the 2nd read register or the instruction's immediate value as the ALU's second operand.", "pt": "Selecciona o valor do 2º registo lido ou o valor imediato da instrução como segundo operando da ALU."}},
		"DistImm":    {"type": "Distributor", "x": 448, "y": 330, "in": {"id": "In", "size": 32}, "out": [{"msb": 31, "lsb": 0}, {"msb": 5, "lsb": 0}]},
		"ALUControl": {"type": "ALUControl", "latency": 50, "x": 456, "y": 330, "aluop": "ALUOp", "func": "func"},
		"ALU":        {"type": "ALU", "latency": 100, "x": 480, "y": 237, "in1": "In1", "in2": "In2", "control": "Operation", "out": "Result", "zero": "Zero"},
		"MuxDst":     {"type": "Multiplexer", "latency": 15, "x": 526, "y": 370, "size": 5, "sel": "RegDst", "in": ["0", "1"], "out": "Out", "desc": {"default": "Selects the instruction's rt or rd field as the destination register (WriteReg).", "pt": "Selecciona o campo rt ou rd da instrução como registo de destino (WriteReg)."}},
		"ShiftImm":   {"type": "ShiftLeft", "x": 465, "y": 190, "in": {"id": "In", "size": 32}, "out": {"id": "Out", "size": 32}, "amount": 2, "desc": {"default": "The 2 less significant bits of the addresses of the instructions are always 00 (the addresses are multiples of 4). As such, these bits are not included in the instruction's immediate value (offset).\nThis component restores those bits by shifting the value 2 bits to the left (or multiplying by 4), in case it is a branch instruction.", "pt": "Os 2 bits menos significativos dos endereços das instruções são sempre 00 (os endereços são múltiplos de 4). Como tal, estes bits não são incluídos no valor imediato da instrução (offset).\nEste componente restaura esses bits deslocando o valor 2 bits para a esquerda (ou multiplicando por 4), no caso de ser uma instrução de branch."}},
		"AddBranch":  {"type": "Add", "latency": 50, "x": 510, "y": 164, "in1": "In1", "in2": "In2", "out": "Out", "desc": {"default": "Adds the branch offset to the PC+4 to obtain the destination branch address, in case it is a branch instruction.", "pt": "Soma o offset do branch ao PC+4 para obter o endereço de destino do branch, no caso de ser uma instrução de branch."}},
		"ForkImm":    {"type": "Fork", "x": 450, "y": 292, "size": 32, "in": "In", "out": ["Out1", "Out2"]},
		"ForkRt2":    {"type": "Fork", "x": 408, "y": 381, "size": 5, "in": "In", "out": ["Out1", "Out2", "Out3"]},
		"ForwardingUnit":{"type": "ForwardingUnit", "latency": 50, "x": 470, "y": 410, "ex_mem_reg_write": "EX/MEM.RegWrite", "mem_wb_reg_write": "MEM/WB.RegWrite", "ex_mem_rd": "EX/MEM.Rd", "mem_wb_rd": "MEM/WB.Rd", "id_ex_rs": "ID/EX.Rs", "id_ex_rt": "ID/EX.Rt", "fwd_a": "ForwardA", "fwd_b": "ForwardB"},
		
		"EX/MEM":     {"type": "PipelineRegister", "x": 550, "y": 110, "regs": {"Result": 32, "ReadData2": 32, "Zero": 1, "RegBankDst": 5, "Target": 32, "Branch": 1, "MemRead": 1, "MemWrite": 1, "MemToReg": 1, "RegWrite": 1}, "desc": {"default": "Register that separates two pipeline stages.\nThe values that transition to the next stage are stored here temporarily.\nIf Flush is active, all values are set to zero, inserting a NOP instruction.", "pt": "Registo que separa duas etapas do pipeline.\nOs valores que transitam para a próxima etapa são armazenados aqui temporariamente.\nSe Flush estiver activo, todos os valores são colocados a zero, inserindo uma instrução NOP."}},
		
		"ForkMem":    {"type": "Fork", "x": 575, "y": 275, "size": 32, "in": "In", "out": ["Out1", "Out2"]},
		"ForkEXR1":   {"type": "Fork", "x": 575, "y": 360, "size": 32, "in": "In", "out": ["Out1", "Out2"]},
		"DataMem":    {"type": "DataMemory", "latency": 400, "x": 580, "y": 242, "size": 100, "address": "Address", "write_data": "WriteData", "out": "ReadData", "mem_read": "MemRead", "mem_write": "MemWrite"},
		"AndBranch":  {"type": "And", "x": 600, "y": 180, "in1": "Branch", "in2": "Zero", "out": "Branch", "desc": {"default": "Determines if a branch should occur.", "pt": "Determina se um branch será efectuado."}},
		"ForkDst1":   {"type": "Fork", "x": 570, "y": 387, "size": 5, "in": "In", "out": ["Out1", "Out2"]},
		"ForkRegWR1": {"type": "Fork", "x": 670, "y": 125, "size": 1, "in": "In", "out": ["Out1", "Out2"]},
		"ForkMemRd":  {"type": "Fork", "x": 420, "y": 140, "size": 1, "in": "In", "out": ["Out1", "Out2"]},
		"ForkBr1":    {"type": "Fork", "x": 555, "y": 62, "size": 1, "in": "In", "out": ["Out1", "Out2"]},
		"ForkBr2":    {"type": "Fork", "x": 397, "y": 62, "size": 1, "in": "In", "out": ["Out1", "Out2"]},
		"ForkBr3":    {"type": "Fork", "x": 185, "y": 62, "size": 1, "in": "In", "out": ["Out1", "Out2"]},
		"OrFlush":    {"type": "Or", "x": 375, "y": 70, "in1": "Stall", "in2": "Branch", "out": "Flush"},
		
		"MEM/WB":     {"type": "PipelineRegister", "x": 680, "y": 110, "regs": {"Result": 32, "ReadData": 32, "RegBankDst": 5, "MemToReg": 1, "RegWrite": 1}, "desc": {"default": "Register that separates two pipeline stages.\nThe values that transition to the next stage are stored here temporarily.", "pt": "Registo que separa duas etapas do pipeline.\nOs valores que transitam para a próxima etapa são armazenados aqui temporariamente."}},
		
		"MuxMem":     {"type": "Multiplexer", "latency": 15, "x": 715, "y": 270, "size": 32, "sel": "MemToReg", "in": ["0", "1"], "out": "Out", "desc": {"default": "Selects the result of the ALU or the value read from memory to write to the destination register (WriteData).", "pt": "Selecciona o resultado da ALU ou o valor lido da memória para escrever no registo de destino (WriteData)."}},
		"ForkRegWR2": {"type": "Fork", "x": 710, "y": 125, "size": 1, "in": "In", "out": ["Out1", "Out2"]},
		"ForkDst2":   {"type": "Fork", "x": 705, "y": 440, "size": 5, "in": "In", "out": ["Out1", "Out2"]},
		"ForkMemR1":  {"type": "Fork", "x": 416, "y": 480, "size": 32, "in": "In", "out": ["Out1", "Out2"]}
	},
	"wires": [
		{"from": "PC", "out": "PC", "to": "ForkPC", "in": "In"},
		{"from": "ForkPC", "out": "Out1", "to": "InstMem", "in": "Address"},
		{"from": "ForkPC", "out": "Out2", "to": "PCAdder", "in": "In1", "points": [{"x": 80, "y": 169}]},
		{"from": "Const4", "out": "Out", "to": "PCAdder", "in": "In2"},
		{"from": "PCAdder", "out": "PC+4", "to": "ForkPCAdder", "in": "In"},
		{"from": "ForkPCAdder", "out": "Out1", "to": "MuxPC", "in": "0", "points": [{"x": 155, "y": 150}, {"x": 10, "y": 150}, {"x": 10, "y": 259}]},
		{"from": "MuxPC", "out": "Out", "to": "PC", "in": "NewPC"},
		{"from": "ForkPCAdder", "out": "Out2", "to": "IF/ID", "in": "NewPC", "end": {"x": 180, "y": 175}},
		{"from": "InstMem", "out": "Instruction", "to": "IF/ID", "in": "Instruction", "end": {"x": 180, "y": 265}},
		
		{"from": "IF/ID", "out": "NewPC", "to": "ID/EX", "in": "NewPC", "start": {"x": 195, "y": 175}, "end": {"x": 390, "y": 175}},
		{"from": "IF/ID", "out": "Instruction", "to": "DistInst", "in": "Instruction", "start": {"x": 195, "y": 265}},
		{"from": "DistInst", "out": "31-26", "to": "Control", "in": "Opcode", "start": {"x": 205, "y": 255}, "points": [{"x": 210, "y": 255}, {"x": 210, "y": 120}]},
		{"from": "DistInst", "out": "25-21", "to": "ForkRs2", "in": "In", "start": {"x": 205, "y": 260}, "points": [{"x": 215, "y": 260}]},
		{"from": "ForkRs2", "out": "Out1", "to": "ForkRs", "in": "In", "points": [{"x": 215, "y": 235}]},
		{"from": "ForkRs2", "out": "Out2", "to": "HazardUnit", "in": "IF/ID.Rs", "points": [{"x": 215, "y": 26}]},
		{"from": "ForkRs", "out": "Out1", "to": "RegBank", "in": "ReadReg1"},
		{"from": "ForkRs", "out": "Out2", "to": "ID/EX", "in": "Rs", "points": [{"x": 230, "y": 372}], "end": {"x": 390, "y": 372}},
		{"from": "DistInst", "out": "20-16", "to": "ForkRt", "in": "In", "start": {"x": 205, "y": 265}},
		{"from": "ForkRt", "out": "Out1", "to": "ForkRt3", "in": "In"},
		{"from": "ForkRt3", "out": "Out1", "to": "RegBank", "in": "ReadReg2"},
		{"from": "ForkRt3", "out": "Out2", "to": "HazardUnit", "in": "IF/ID.Rt", "points": [{"x": 220, "y": 42}]},
		{"from": "ForkRt", "out": "Out2", "to": "ID/EX", "in": "Rt", "points": [{"x": 220, "y": 381}], "end": {"x": 390, "y": 381}},
		{"from": "DistInst", "out": "15-0", "to": "ExtendImm", "in": "In", "start": {"x": 205, "y": 270}, "points": [{"x": 225, "y": 270}, {"x": 225, "y": 350}]},
		{"from": "DistInst", "out": "15-11", "to": "ID/EX", "in": "Rd", "start": {"x": 205, "y": 275}, "points": [{"x": 215, "y": 275}, {"x": 215, "y": 392}], "end": {"x": 390, "y": 392}},
		{"from": "RegBank", "out": "ReadData1", "to": "ID/EX", "in": "ReadData1", "end": {"x": 390, "y": 248}},
		{"from": "RegBank", "out": "ReadData2", "to": "ID/EX", "in": "ReadData2", "end": {"x": 390, "y": 281}},
		{"from": "ExtendImm", "out": "Out", "to": "ID/EX", "in": "Imm", "end": {"x": 390, "y": 350}},
		{"from": "Control", "out": "ALUOp", "to": "ID/EX", "in": "ALUOp", "start": {"x": 290, "y": 160}, "end": {"x": 390, "y": 160}},
		{"from": "Control", "out": "ALUSrc", "to": "ID/EX", "in": "ALUSrc", "start": {"x": 290, "y": 155}, "end": {"x": 390, "y": 155}},
		{"from": "Control", "out": "RegDst", "to": "ID/EX", "in": "RegDst", "start": {"x": 290, "y": 150}, "end": {"x": 390, "y": 150}},
		{"from": "Control", "out": "Branch", "to": "ID/EX", "in": "Branch", "start": {"x": 290, "y": 145}, "end": {"x": 390, "y": 145}},
		{"from": "Control", "out": "MemRead", "to": "ID/EX", "in": "MemRead", "start": {"x": 290, "y": 140}, "end": {"x": 390, "y": 140}},
		{"from": "Control", "out": "MemWrite", "to": "ID/EX", "in": "MemWrite", "start": {"x": 290, "y": 135}, "end": {"x": 390, "y": 135}},
		{"from": "Control", "out": "MemToReg", "to": "ID/EX", "in": "MemToReg", "start": {"x": 290, "y": 130}, "end": {"x": 390, "y": 130}},
		{"from": "Control", "out": "RegWrite", "to": "ID/EX", "in": "RegWrite", "start": {"x": 290, "y": 125}, "end": {"x": 390, "y": 125}},
		{"from": "HazardUnit", "out": "Stall", "to": "ForkStall", "in": "In"},
		{"from": "ForkStall", "out": "Out1", "to": "OrFlush", "in": "Stall", "points": [{"x": 382, "y": 5}], "end": {"x": 382, "y": 70}},
		{"from": "OrFlush", "out": "Flush", "to": "ID/EX", "in": "Flush", "start": {"x": 395, "y": 100}},
		{"from": "ForkStall", "out": "Out2", "to": "NotStall", "in": "Stall", "end": {"x": 205, "y": 5}},
		{"from": "NotStall", "out": "Write", "to": "ForkWrite", "in": "In", "start": {"x": 190, "y": 32}},
		{"from": "ForkWrite", "out": "Out1", "to": "IF/ID", "in": "Write"},
		{"from": "ForkWrite", "out": "Out2", "to": "PC", "in": "Write", "points": [{"x": 55, "y": 50}]},
		
		{"from": "ID/EX", "out": "ReadData1", "to": "MuxFwdA", "in": "0", "start": {"x": 405, "y": 248}, "end": {"x": 425, "y": 248}},
		{"from": "MuxFwdA", "out": "Out", "to": "ALU", "in": "In1", "start": {"x": 440, "y": 250}, "end": {"x": 480, "y": 250}},
		{"from": "ID/EX", "out": "ReadData2", "to": "MuxFwdB", "in": "0", "start": {"x": 405, "y": 281}, "end": {"x": 425, "y": 281}},
		{"from": "MuxFwdB", "out": "Out", "to": "ForkReg", "in": "In", "start": {"x": 440, "y": 281}},
		{"from": "ForkEXR2", "out": "Out2", "to": "MuxFwdB", "in": "2"},
		{"from": "ForkMEMR2", "out": "Out2", "to": "MuxFwdB", "in": "1"},
		{"from": "ForkReg", "out": "Out1", "to": "MuxReg", "in": "0"},
		{"from": "ForkReg", "out": "Out2", "to": "EX/MEM", "in": "ReadData2", "points": [{"x": 445, "y": 308}], "end": {"x": 550, "y": 308}},
		{"from": "MuxReg", "out": "Out", "to": "ALU", "in": "In2", "end": {"x": 480, "y": 287}},
		{"from": "ID/EX", "out": "ALUSrc", "to": "MuxReg", "in": "ALUSrc", "start": {"x": 405, "y": 155}, "points": [{"x": 462, "y": 155}]},
		{"from": "ID/EX", "out": "Imm", "to": "DistImm", "in": "In", "start": {"x": 405, "y": 350}, "end": {"x": 448, "y": 350}},
		{"from": "ALUControl", "out": "Operation", "to": "ALU", "in": "Operation", "points": [{"x": 510, "y": 350}]},
		{"from": "DistImm", "out": "5-0", "to": "ALUControl", "in": "func", "start": {"x": 448, "y": 350}},
		{"from": "ID/EX", "out": "ALUOp", "to": "ALUControl", "in": "ALUOp", "start": {"x": 405, "y": 160}, "points": [{"x": 446, "y": 160}, {"x": 446, "y": 235}, {"x": 476, "y": 235}]},
		{"from": "ALU", "out": "Zero", "to": "EX/MEM", "in": "Zero", "start": {"x": 540, "y": 255}, "end": {"x": 550, "y": 255}},
		{"from": "ALU", "out": "Result", "to": "EX/MEM", "in": "Result", "start": {"x": 540, "y": 275}, "end": {"x": 550, "y": 275}},
		{"from": "ID/EX", "out": "Rt", "to": "ForkRt2", "in": "In", "start": {"x": 405, "y": 381}},
		{"from": "ForkRt2", "out": "Out1", "to": "MuxDst", "in": "0"},
		{"from": "ForkRt2", "out": "Out2", "to": "ForwardingUnit", "in": "ID/EX.Rt", "points": [{"x": 408, "y": 442}]},
		{"from": "ForkRt2", "out": "Out3", "to": "HazardUnit", "in": "ID/EX.Rt", "points": [{"x": 408, "y": 42}]},
		{"from": "ID/EX", "out": "Rd", "to": "MuxDst", "in": "1", "start": {"x": 405, "y": 392}},
		{"from": "ID/EX", "out": "RegDst", "to": "MuxDst", "in": "RegDst", "start": {"x": 405, "y": 150}, "points": [{"x": 547, "y": 150}, {"x": 547, "y": 365}, {"x": 533, "y": 365}]},
		{"from": "MuxDst", "out": "Out", "to": "EX/MEM", "in": "RegBankDst", "end": {"x": 550, "y": 387}},
		{"from": "ID/EX", "out": "NewPC", "to": "AddBranch", "in": "In1", "start": {"x": 405, "y": 175}},
		{"from": "DistImm", "out": "31-0", "to": "ForkImm", "in": "In", "start": {"x": 450, "y": 330}},
		{"from": "ForkImm", "out": "Out1", "to": "MuxReg", "in": "1"},
		{"from": "ForkImm", "out": "Out2", "to": "ShiftImm", "in": "In", "points": [{"x": 450, "y": 210}]},
		{"from": "ShiftImm", "out": "Out", "to": "AddBranch", "in": "In2", "points": [{"x": 507, "y": 210}, {"x": 507, "y": 186}]},
		{"from": "AddBranch", "out": "Out", "to": "EX/MEM", "in": "Target", "end": {"x": 550, "y": 181}},
		{"from": "ID/EX", "out": "Branch", "to": "EX/MEM", "in": "Branch", "start": {"x": 405, "y": 145}, "end": {"x": 550, "y": 145}},
		{"from": "ID/EX", "out": "MemRead", "to": "ForkMemRd", "in": "In", "start": {"x": 405, "y": 140}},
		{"from": "ForkMemRd", "out": "Out1", "to": "EX/MEM", "in": "MemRead", "end": {"x": 550, "y": 140}},
		{"from": "ForkMemRd", "out": "Out2", "to": "HazardUnit", "in": "ID/EX.MemRead", "points": [{"x": 420, "y": 26}]},
		{"from": "ID/EX", "out": "MemWrite", "to": "EX/MEM", "in": "MemWrite", "start": {"x": 405, "y": 135}, "end": {"x": 550, "y": 135}},
		{"from": "ID/EX", "out": "MemToReg", "to": "EX/MEM", "in": "MemToReg", "start": {"x": 405, "y": 130}, "end": {"x": 550, "y": 130}},
		{"from": "ID/EX", "out": "RegWrite", "to": "EX/MEM", "in": "RegWrite", "start": {"x": 405, "y": 125}, "end": {"x": 550, "y": 125}},
		{"from": "ID/EX", "out": "Rs", "to": "ForwardingUnit", "in": "ID/EX.Rs", "start": {"x": 405, "y": 372}, "points": [{"x": 413, "y": 372}, {"x": 413, "y": 426}]},
		{"from": "ForwardingUnit", "out": "ForwardA", "to": "MuxFwdA", "in": "ForwardA", "points": [{"x": 493, "y": 400}, {"x": 441, "y": 400}, {"x": 441, "y": 270}, {"x": 432, "y": 270}], "end": {"x": 432, "y": 265}},
		{"from": "ForwardingUnit", "out": "ForwardB", "to": "MuxFwdB", "in": "ForwardB", "points": [{"x": 516, "y": 405}, {"x": 432, "y": 405}], "end": {"x": 432, "y": 310}},
		
		{"from": "EX/MEM", "out": "RegBankDst", "to": "ForkDst1", "in": "In", "start": {"x": 565, "y": 387}},
		{"from": "ForkDst1", "out": "Out1", "to": "MEM/WB", "in": "RegBankDst", "end": {"x": 680, "y": 387}},
		{"from": "ForkDst1", "out": "Out2", "to": "ForwardingUnit", "in": "EX/MEM.Rd", "points": [{"x": 570, "y": 420}]},
		{"from": "EX/MEM", "out": "Result", "to": "ForkMem", "in": "In", "start": {"x": 565, "y": 275}},
		{"from": "ForkMem", "out": "Out1", "to": "DataMem", "in": "Address"},
		{"from": "ForkMem", "out": "Out2", "to": "ForkEXR1", "in": "In"},
		{"from": "ForkEXR1", "out": "Out1", "to": "MEM/WB", "in": "Result", "end": {"x": 680, "y": 360}},
		{"from": "ForkEXR1", "out": "Out2", "to": "ForkEXR2", "in": "In", "points": [{"x": 575, "y": 462}, {"x": 421, "y": 462}]},
		{"from": "ForkEXR2", "out": "Out1", "to": "MuxFwdA", "in": "2", "points": [{"x": 421, "y": 259}], "end": {"x": 425, "y": 259}},
		{"from": "EX/MEM", "out": "ReadData2", "to": "DataMem", "in": "WriteData", "start": {"x": 565, "y": 308}},
		{"from": "DataMem", "out": "ReadData", "to": "MEM/WB", "in": "ReadData", "end": {"x": 680, "y": 292}},
		{"from": "EX/MEM", "out": "Target", "to": "MuxPC", "in": "1", "start": {"x": 565, "y": 181}, "points": [{"x": 575, "y": 181}, {"x": 575, "y": 67}, {"x": 5, "y": 67}, {"x": 5, "y": 270}]},
		{"from": "EX/MEM", "out": "Zero", "to": "AndBranch", "in": "Zero", "start": {"x": 565, "y": 255}, "points": [{"x": 572, "y": 255}, {"x": 572, "y": 200}]},
		{"from": "EX/MEM", "out": "Branch", "to": "AndBranch", "in": "Branch", "start": {"x": 565, "y": 145}, "points": [{"x": 580, "y": 145}, {"x": 580, "y": 190}]},
		{"from": "AndBranch", "out": "Branch", "to": "ForkBr1", "in": "In", "points": [{"x": 640, "y": 195}, {"x": 640, "y": 62}]},
		{"from": "ForkBr1", "out": "Out1", "to": "ForkBr2", "in": "In"},
		{"from": "ForkBr1", "out": "Out2", "to": "EX/MEM", "in": "Flush"},
		{"from": "ForkBr2", "out": "Out1", "to": "ForkBr3", "in": "In"},
		{"from": "ForkBr2", "out": "Out2", "to": "OrFlush", "in": "Branch", "end": {"x": 397, "y": 70}},
		{"from": "ForkBr3", "out": "Out1", "to": "MuxPC", "in": "PCSrc", "points": [{"x": 22, "y": 62}]},
		{"from": "ForkBr3", "out": "Out2", "to": "IF/ID", "in": "Flush"},
		{"from": "EX/MEM", "out": "MemRead", "to": "DataMem", "in": "MemRead", "start": {"x": 565, "y": 140}, "points": [{"x": 590, "y": 140}], "end": {"x": 590, "y": 242}},
		{"from": "EX/MEM", "out": "MemWrite", "to": "DataMem", "in": "MemWrite", "start": {"x": 565, "y": 135}, "points": [{"x": 650, "y": 135}], "end": {"x": 650, "y": 242}},
		{"from": "EX/MEM", "out": "MemToReg", "to": "MEM/WB", "in": "MemToReg", "start": {"x": 565, "y": 130}, "end": {"x": 680, "y": 130}},
		{"from": "EX/MEM", "out": "RegWrite", "to": "ForkRegWR1", "in": "In", "start": {"x": 565, "y": 125}},
		{"from": "ForkRegWR1", "out": "Out1", "to": "MEM/WB", "in": "RegWrite", "end": {"x": 680, "y": 125}},
		{"from": "ForkRegWR1", "out": "Out2", "to": "ForwardingUnit", "in": "EX/MEM.RegWrite", "points": [{"x": 670, "y": 430}]},
		
		{"from": "MEM/WB", "out": "ReadData", "to": "MuxMem", "in": "1", "start": {"x": 695, "y": 292}},
		{"from": "MEM/WB", "out": "Result", "to": "MuxMem", "in": "0", "start": {"x": 695, "y": 360}, "points": [{"x": 702, "y": 360}, {"x": 702, "y": 281}]},
		{"from": "MEM/WB", "out": "MemToReg", "to": "MuxMem", "in": "MemToReg", "start": {"x": 695, "y": 130}, "points": [{"x": 722, "y": 130}]},
		{"from": "MEM/WB", "out": "RegBankDst", "to": "ForkDst2", "in": "In", "start": {"x": 695, "y": 387}, "points": [{"x": 705, "y": 387}]},
		{"from": "ForkDst2", "out": "Out1", "to": "RegBank", "in": "WriteReg", "points": [{"x": 705, "y": 470}, {"x": 250, "y": 470}, {"x": 250, "y": 275}], "end": {"x": 260, "y": 275}},
		{"from": "ForkDst2", "out": "Out2", "to": "ForwardingUnit", "in": "MEM/WB.Rd"},
		{"from": "MuxMem", "out": "Out", "to": "ForkMemR1", "in": "In", "points": [{"x": 735, "y": 287}, {"x": 735, "y": 480}]},
		{"from": "ForkMemR1", "out": "Out1", "to": "RegBank", "in": "WriteData", "points": [{"x": 240, "y": 480}, {"x": 240, "y": 295}], "end": {"x": 260, "y": 295}},
		{"from": "ForkMemR1", "out": "Out2", "to": "ForkMEMR2", "in": "In"},
		{"from": "ForkMEMR2", "out": "Out1", "to": "MuxFwdA", "in": "1", "points": [{"x": 416, "y": 253}], "end": {"x": 425, "y": 253}},
		{"from": "MEM/WB", "out": "RegWrite", "to": "ForkRegWR2", "in": "In", "start": {"x": 695, "y": 125}},
		{"from": "ForkRegWR2", "out": "Out1", "to": "RegBank", "in": "RegWrite", "points": [{"x": 710, "y": 105}, {"x": 300, "y": 105}]},
		{"from": "ForkRegWR2", "out": "Out2", "to": "ForwardingUnit", "in": "MEM/WB.RegWrite", "points": [{"x": 710, "y": 450}]}
	],
	"reg_names": ["zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra"],
	"instructions": "default-no-jump.set"
}
