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# Using Make - part 2

- Make's internal macros
- Tutorial 1
- Tutorial 2
- Summary

## Make's internal macros

## @ Current target

This is a reference to the target of the current rule. It is a macro so we use the $ symbol ala $@ to refer to its value. Since it is only a single character we don't need to enclose it in braces or parentheses.

    APPNAME = mods
    TARGET = $(APPNAME).exe
    OBJECTS = $(APPNAME).o m1.o m2.o

    ${TARGET}: ${OBJECTS}
    	@echo Building $@ with ${OBJECTS}
    	$(CC) -o $@ ${OBJECTS}
    ...

The example shows how we can use $@.

The example shows how we can use $@. Note that the example is incomplete.

## < First dependency

The < internal macro will take the value of the first dependency for the current rule. Refer to it as $<

    APPNAME = mods
    TARGET = $(APPNAME).exe
    OBJECTS = m1.o m2.o

    ${TARGET}: ${OBJECTS}
    	@echo Building $@ with $^
    	$(CC) -o $@ $^
    m1.o: m1.cc m1.h m99.h
    	@echo Building $@ with $<
    	$(CC) -c $<
    ...

This example shows the use of < and ^ which is the dependency list reference which follows.

## ^ All dependencies

The ^ internal macro takes the value the of dependency list for the current rule.

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## Tutorial 1

Exercise 1.1 Exercise 1.2

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## Tutorial 2

Exercise 2.1

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## Summary

There is much that make can do and it isn't limited only to building programs. However I am still learning about it myself so you know as much as I do.

I suggest you read GNU Make : A Program for Directing Recompilation and when you understand all of it you will know as much as the experts do. When you reach that point come and explain it to me.

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Copyright © 1999 - 2001 David Beech