Electric has the concept of a current technology which is shown in the status bar. This technology affects many things, including the selection of nodes and arcs in the component menu. There are a number of ways to affect the current technology, both manual and automatic.

You can change the current technology by selecting it from the popup at the top of the side bar (either the "Components" or "Layers" tab). Electric automatically switches the current technology to match the cell being edited. If there are multiple cells being edited from different technologies, this switching can become annoying. To disable automatic technology switching, use the Nodes Preferences (in menu File / Preferences..., "General" section, "Nodes" tab), and uncheck "Switch technology to match current cell".

To see a list of primitive nodes and arcs in the current technology, use the Describe this Technology command (in menu Edit / Technology Specific). To see a detailed description of the current technology, use the Document Current Technology command.

Some technologies have preferences that further customize them. The Technology Preferences command (in menu File / Preferences..., "Technology" section, "Technology" tab) lets you control many User and Project preferences. The Project Preferences are on the left, and the bottom part of the Project Preferences is specific to the MOSIS CMOS technology. More information about this can be found in Section 7-4-2.

The Defaults section at the top of the Project Preferences section has these controls:

- "Startup technology" controls the technology that is used when Electric first begins. It is also used when reading old libraries that are missing some technology information.
- "Layout technology to use for Schematics" sets the technology to use for real geometry (an integrated circuit technology, not a schematics or artwork technology). The default layout technology is used to give further information about schematics components (see, for example, Section 9-4-3).
- "PSubstrate process in Layout Technology" declares that the layout technologies use P Substrate (NWell), and therefore the PWell spacing and minimum width rules should be ignored by the design-rule checker. Since Electric displays both wells, users might be concerned with filling in notches in the PWell, but in these processes it is not necessary.

The User Preferences section is discussed elsewhere For information about rotating transistors in the menus, see Section 7-4-2. For information about Schematic primitive names, see Section 7-5-1 and Section 3-11-2.