A technology is an environment in which design is done. Technologies can be layout specific, for example MOSIS CMOS, or they can be abstract, for example Schematics and Artwork. There are multiple CMOS variations to handle popular design rules such as MOSIS, submicron, etc.

Each technology consists of a set of primitive nodes and arcs. These, in turn, are constructed from one or more layers. Each technology also includes information necessary to do design, such as design rules, connectivity rules, simulation information, etc.

The primitive nodes in a technology come in three styles:

- PINS are used to join arcs, so there is one pin for every arc in the technology.
- COMPONENTS are the basic nodes used in design: contacts, transistors, etc.
- PURE-LAYER NODES are used for geometric manipulation (see Section 6-10-1). There is one pure-layer node for every layer in the technology.

The component menu in the side bar (on the left side of the editing window) shows arcs on the left (the menu entries with red border), pin nodes in the center column (these appear as boxes with a cross inside), and components on the right (the more complex layer combinations). See Section 4-5-1 for more on the component menu.

These are the technologies that come with Electric. Some of these technologies are illustrated with sample cells in the built-in "sample" library. To access this library, use the Load Sample Cells Library command (in menu Help).

- artwork is used for drawing graphics, for example when designing icons. See Section 7-6-1 for more. The cell `tech-Artwork` in the sample library illustrates this technology.
- bicmos a hybrid bipolar/CMOS technology, as specified by MOSIS using older N-Well SCE rules.
- bipolar a bipolar technology (self-aligned, single-poly). The cell `tech-Bipolar{lay}` in the sample library illustrates this technology.
- cmos a generic CMOS technology described in a old paper (Griswold, Thomas W., "Portable Design Rules for Bulk CMOS," VLSI Design, III:5, 62-67, September/October 1982). It was never aligned with an actual process and exists only for illustration.
- efido a high-level digital-filter architecture technology. The cell `tech-DigitalFilter` in the sample library illustrates this technology.
- fpga a customizable technology that can describe field-programmable gate array architectures. The basic technology does not have any FPGA capabilities: it must be customized with a special architecture file (see Section 7-6-2 for more).
- gem a temporal-logic technology that illustrates Electric's capability to do graph editing in nonelectrical environments. Based on the paper: Lansky, A. L. and Owicki, S. S., "GEM: A Tool for Concurrency Specification and Verification," Proceedings 2nd Annual ACM Symposium on Principles of Distributed Computing, 198-212, August 1983. The cell `tech-Gem` in the sample library illustrates this technology.
- generic a technology used for special features such as inter-technology connections, routing specifications, cell definitions, etc. This technology is never used for actual design, but its nodes and arcs appear in many places. See Section 7-6-3 for more.
- mocmos a CMOS technology that conforms to MOSIS design rules. This is the most used CMOS technology in Electric, because it is kept current with MOSIS rules. See Section 7-4-2 for more. The cell `tech-MOSISCMOS{lay}` in the sample library illustrates this technology.
- mocmosold an older version of the "mocmos" technology, kept for compatibility with older designs. The technology should not be used for any new designs.
- mocmossub an older version of the "mocmos" technology that focuses on submicron facilities. The technology should not be used for any new designs because the "mocmos" technology incorporates these submicron features.
- nmos an old nMOS technology, based on the book: Mead, C. and Conway, L., Introduction to VLSI Systems, Addison-Wesley, Reading, Massachusetts, 1980. The cell `tech-nMOS{lay}` in the sample library illustrates this technology.
- pcb a printed-circuit board technology with 8 layers. The cell `tech-PCB{sch}` in the sample library illustrates this technology.
- rcmos a round CMOS technology, based on work at CalTech. The cell `tech-RoundCMOS{lay}` in the sample library illustrates this technology.
- schematic a schematic capture facility. See Section 7-5-1 for more. The cells `tech-SchematicsDigital{sch}` and `tech-SchematicsAnalog{sch}` in the sample library illustrates the digital and analog capabilities of this technology.
- tft an organic thin-film technology. Thin film transistors are p-type depletion devices formed with an aluminum gate, gold source/drain electrodes, and a pentacene active area. Two layers of metal are available for routing signals, Metal-1 (the aluminum gate metal) and Metal-2 (the source/drain metal). A capacitor is also available in the process and is formed between the gate electrode and a source/drain electrode. The cell `tech-TFTInverter{lay}` in the sample library illustrates this technology.