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bladeRF HDL Change Log Summary

For more detailed information, please see the git change log and issue tracker
hosted on GitHub: https://github.com/nuand/bladeRF
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v0.7.1 (2017-12-07)
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 * Minor fix-ups

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v0.7.0 (2017-07-02)
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 * Added support for the Automatic Gain Control

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v0.6.0 (2015-05-25)
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 * Added TRX synchronization trigger functionality via J71-4.

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v0.5.0 (2015-11-23)
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 * Added support for 1 PPS and 10 MHz input to tame VCTCXO
 * Added FIFO between TX and RX for digital loopback mode for clock
   synchronization and additional sample buffering.

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v0.4.1 (2015-09-01)
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 * Fixed bug in XB GPIO masked writes introduced in v0.4.0

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v0.4.0 (2015-08-27)
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 * Added support for multi-write of TX and RX NINT/NFRAC registers
    - LMS6002D PLL registers are written atomically to allow for
      slightly cleaner retuning.

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v0.3.5 (2015-08-25)
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 * Build and simulation fixes

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v0.3.4 (2015-07-24)
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 * Fixed a bug where multiple TX NOW bursts would accumulate samples
   in the RX FIFO and was causing a slip in metadata headers versus samples.
 * Modified sample FIFOs to have under/overflow checking
 * Register FIFO reader output
 * Addressed some warnings about latches.
 * Build fixes for atsc_tx image 

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v0.3.3 (2015-06-30)
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 * Addressed timing constraint issue by reducing LMS SPI clock rate.
 * Renamed SPI controller module

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v0.3.2 (2015-06-23)
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 * Fixed VCTCXO readback

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v0.3.1 (2015-06-17)
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 * Added faster, custom SPI block for LMS6 communication.
    - This custom block removes large gaps of time between CSn and the clocking
      of data, as well as gaps of time between bytes.

v0.3.0 (2015-06-17)
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 This version is part of development series of changes, not an official release.

 * Added support for the following packet formats.
    - pkt_8x8
    - pkt_8x16
    - pkt_8x32
    - pkt_8x64
    - pkt_32x32

   For more information about these packet formats, see:
    bladeRF/hdl/fpga/ip/altera/nios_system/software/bladeRF_nios/README.md

v0.2.0 (2015-06-17)
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 This version is part of development series of changes, not an official release.

 * Build updated for Quartus II 15.0
    - Earlier Quartus versions are not compatible.

 * Redesigned control/configuration program running on NIOS II
    - This introduces support for different packet formats for
      NIOS II <-> host communication.
    - Readability and performance improvements

 * The time tamers have been separated and now have programmable interrupts.

 * Added tuning support:
    - The LMS6 VCOCAP search can now be performed in the NIOS,
      cutting out overhead incurred when performing all register accesses
      via the host.
    - A "Quick tune" option allows the LMS6 to be tuned using previously
      determined settings, instead of running the full tuning algorithm.
    - Introduced scheduled retune support


v0.1.2 (2014-10-22)
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 * Fixed issues with TX_NOW and dropped messages. This fixes issues
   #334 and #335.

v0.1.1 (2014-10-22)
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 * Fixed timing errors that caused failures in SPI communication with the
   LMS6002D. This addresses the LMS calbration failure assocaited with issue
   #269.

v0.1.0 (2014-10-21)
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 * Backwards-compatible features introduced:
    - Added option to divide sample counter by 2.
    - Added "TX_NOW"

 * Fixes:
    - Addessed data/timestamp slipping
    - Fixed readback of current timestamp value
    - Send zero samples TX module to mitigate effect of default output power
      from the LMS after intialization.


v0.0.6 (2014-07-20)
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 * Fixed FPGA correction for gain/phase

v0.0.5 (2014-06-21)
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 * Added expansion board support for XB-200


v0.0.4 (2014-05-07)
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 * Added metadata timestamp support
    - Added RX/TX metadata FIFOs
 * Added FPGA digital loopback


v0.0.3 (2014-02-01)
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 * Tweaked constraints for FX3 interface drive strength
 * Add 32-bit counter mode for RX performance testing


v0.0.2 (2014-01-14)
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 * Tweaked constraints for the FX3 interface
 * Fixed SPI/UART signal contention issue
 * Fixed phase range for IQ correction block


v0.0.1 (2013-12-28)
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 * Updated to use Quartus 13.1 tools
    - Renamed OpenCores I2C Qsys core to not conflict
 * Introduced faster UART bridge (4Mbps versus 115.2kbps)
 * Added IQ correction block
 * Added FPGA version numbering
 * Made FX3 GPIF FSM more maintainable
